Função Fisicamente Inclonável como algoritmo de cibersegurança embarcado em FPGA

Abstract

This work presents the implementation of an Arbiter Physically Unclonable Function (Arbiter PUF or APUF) algorithm on a system based on a Field-Programmable Gate Array (FPGA). With the rise of the Internet of Things (IoT) and the widespread adoption of Artificial Intelligence (AI) across various technological domains, there is an increasing demand for digital security mechanisms tailored to the performance and resource constraints of such systems. In this context, the project was primarily based on the methodology described in [1], which outlines an implementation of an XOR-APUF on FPGA. The development was carried out using Quartus II 13.0 and ModelSim software tools, along with the Altera DE2 development board, enabling both simulation and practical validation of the proposed algorithm. During the implementation process, several adaptations to the original reference were required due to hardware and software differences that prevented direct replication. This work provides a detailed explanation of the operation of an APUF embedded in FPGA, serving as a technical and educational reference for researchers and developers. As a key contribution, the project demonstrates the feasibility of using FPGAs to deploy PUF-based security protocols in IoT applications, while also contributing to the training of qualified personnel and promoting research initiatives in the field of embedded cybersecurity.