Simulador funcional de memórias cache para fins didáticos

Abstract

This paper presents CacheLab, a functional cache memory simulator developed to support the teaching of Computer Architecture in undergraduate Computer Science courses. In addition to allowing the parameterization of cache designs at various levels, the difference between this simulator and others with the same purpose is that CacheLab simulates cache behavior using memory traces generated from real applications, instead of simulating accesses to random addresses. The tool is optimized to allow low resource utilization during simulations, allowing the evaluation of caches with virtually unlimited size.