Geração Procedural de Redes Neurais Flexíveis em VHDL para Aceleração em FPGA

Abstract

With the increasing demand for efficient Artificial Intelligence solutions, hardware acceleration using Field-Programmable Gate Arrays (FPGAs) has emerged as a powerful alternative to traditional software implementations. However, a significant limitation in many VHDL-based Neural Network designs is their static nature, where the network topology is fixed in the source code, restricting scalability and reuse. To address this rigidity, this work proposes a methodology for the procedural generation of flexible Multi-Layer Perceptron (MLP) architectures. Using VHDL generic parameters and generate statements, the proposed system allows the dynamic instantiation of layers and neurons at synthesis time, enabling rapid prototyping without manual code rewriting. The architecture utilizes fixed-point arithmetic (Q16.16) and offline training in Python to optimize hardware resources. Validation was performed through simulations using ModelSim and synthesis via Intel Quartus II, targeting a Cyclone IV GX device. The results demonstrated a bit-perfect match between the hardware simulation and the software reference model for an XOR problem. Although the generic architecture incurred a higher resource utilization (21\% of Logic Elements) compared to a static equivalent (17\%), the study concludes that this trade-off is justified by the significant gain in flexibility, allowing for the efficient reconfiguration of neural network topologies.